GBSelfTest

Every expectation is one of two things.

• Computed a second, independent way on the machine itself. The adder is checked against a counter built from INC HL, which sets no flags and goes through a different unit. The logic operations are checked against De Morgan's law. The rotates are checked by the fact that eight of them are the identity. DAA is checked against decimal arithmetic done a digit at a time
• A documented constant that is a fact about the hardware — a register's read-back mask, an instruction's published cycle count, the 456 cycles in a scanline
• A behaviour that can be checked neither way is listed as untested, with the reason, in the coverage statement the cartridge prints at the end of every run

• The screen is 20 columns by 18 rows, so it carries the area verdicts and a list of codes. The link port carries the whole story
• Each failure names what it saw, what it wanted, a hypothesis about the missing behaviour in hardware terms, and a URL
• Codes are never reused and never renumbered, so one printed by a two-year-old build still means what it meant
• A host that only wants the verdict can stop at Passed or Failed — Blargg's convention, so an existing runner needs no changes

• A cartridge cannot see the screen. But mode 3 lasts exactly as long as the fetcher takes, and the fetcher takes longer when there is more to draw
• So the cartridge lays out a scene whose cost is documented and measures how long mode 3 actually took — a real test of rendering with no reference image in it
• A coincidence interrupt is armed on one scanline; the handler runs a variable number of NOPs before reading STAT once, and a binary search finds the machine cycle the mode changes on. The delay from interrupt to first NOP is unknown and does not matter, because every result is the difference between two edges
• In practice this is the most discriminating thing here: it separates a renderer that draws a whole line at once from one that models the fetcher

An emulator that advances its peripherals once per instruction still runs every clock at the right rate. The frame is still 70,224 cycles, the timer still ticks correctly, the interrupt still arrives exactly once. Nothing measured over a run of instructions can see it. Two checks look at phase inside an instruction instead:

• GB-CYC-07 reads one register twice from the same starting phase, once with a three-cycle instruction and once with a four-cycle one. Over four one-cycle delays the longer must overtake the shorter exactly once. A batched machine sees both reads at the instruction's start, and it never overtakes
• GB-CYC-08 lets the timer overflow inside a sled of NOPs and has the handler read the return address, which names the instruction the interrupt landed on. Entering one cycle later must move that landing back by one instruction, eight times over. On a batched machine the landing stops moving